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Verification IP
test and verify SoC's protocols and interface buses.
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MIPI Soundwire Total IP Solutions
Soundwire
Soundwire is suited for small, cost-sensitive audio peripherals such as modern digital class-D amplifiers and digital microphones. The Total MIPI SoundWire IP Solution from Arasan enables early adopters the fastest path to adoption of this new standard by offering a comprehensive IP package that includes the Verilog RTL source code for Master and Slave, fully validated for compliance with the standard, a comprehensive test environment with a compliance suite for verification of the IP package, a SoundWire Hardware Development Kit (“HDK”) for FPGA prototyping, a SoundWire protocol analyzer and a complete SoundWire software stack.
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Waterproof Test Chamber
JL-XC
JL-XC series waterproof test chamber is mainly used for small electronic and electrical products. Such as lamps, electrical cabinets, electrical components and so one. The products are tested for physical and other related properties under simulated climatic conditions. After the test, it is judged whether the performance of the product meets the requirements by verification, so as to be used in the design, improvement, verification and factory inspection of the product. Comply with IEC60529:2001 《Degrees of protection provided by enclosures (IP Code)》, GB4208-2008 《Shell Protection Grade (IP Code)》 14.2.8 Terms and GB7000.1 《Lamps Part 1: General Requirements and Tests》 9.2.9 Terms.
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EMBEDDED MMC (EMMC)
SD 3.0 / eMMC 4.51 IP Family
The eMMC Host IP is an RTL design in Verilog that implements an MMC / eMMC host controller in an ASIC or FPGA. The core includes RTL code, test scripts and a test environment for full simulation verifications. The Arasan MMC / eMMC Host IP Core has been widely used in different MMC applications by major semiconductor vendors with proven silicon.
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MIPI Total Display IP Solution
DSI
The Arasan MIPI Display Serial Interface (DSI) Controller IP provides both device and host functionality. Additionally, the DSI Controller provides a high-speed serial interface between an application processor and display and follows a rigorous verification methodology to ensure interoperability of our DSI digital controller with our D-PHY analog IP. Arasan’s DSI solutions are MIPI standards-compliant and are designed to accelerate integration, lower risk and accelerate time to market for developers of display applications. Arasan’s expertise is backed by our unique silicon proven design discipline and product development process that ensures fast silicon success with our analog and digital IP.
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ADSL / 2 / 2+ Handheld VoIP Tester
QuickTest 500
*Rapid Testing. The QuickTest 500 ADSL2+ Tester's automatic Service Verification Test Suite starts as soon as you switch on (results are typically obtained in less than 3 minutes)*Simple to use. Virtually no product training required with QuickTest 500 ADSL Tester*Configurable Pass / Fail Indicators on the LCD display and clearly presented in multi-colour LEDs on the front panel*No need to get a laptop out*Save and name up to 16 test results at any one time*Line Voltage LED indicates poor, missing or excessive Line Voltage*ADSL/2/2+ Test LEDs to indicate if ADSL Showtime achieved*In Service LED indicates problems with PPP or IP layer*LEDs to indicate problems with the Trained Line Rate, poor Noise Margin or excessive Line Attenuation
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Ethernet Testing Network Performance
Networked Communication Solutions, LLC
Xena Networks and Veryx Technologies have created an innovative Ethernet test platform that combines Xena’s high performance, wire-speed Ethernet test hardware with Veryx’s broad portfolio of IP & Ethernet functional and conformance test suites. The result: an affordable, high-performance platform for IP & Ethernet load stress, protocol conformance & functional verification testing.
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IP Reuse
IC Manage Global Design Platform (GDP & GDP-XL) includes an open platform for maximizing IP reuse. Design and verification teams can use the system to rapidly publish and integrate IP into existing flows, and to trace bug dependencies. Internal and third party IP can be imported or linked with IP Central from multiple commercial and open source design management systems, as well as internal revision control systems. ”
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Field Ttesters
Our product range comprises from small handheld, battery fed testers to full featured service performance assurance tools and distributed monitoring systems. We have several product lines including:QoS / SLA verification system Ethernet, IP, Critical Data, VoIP, IPTV .Hand-held testers: Gigabit Ethernet, Synchronous Ethernet, E1, PDH, SDH, Ethernet, IP, Jitter, Wander, Datacom, Frame Relay, etc.
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Analyze RTL
ASICs and FPGA routinely have millions of gates with memories, transceivers, third party IP and processor cores. Problems can be time consuming and complex to debug in the lab and through simulations. Designers need verification tools that can identify problems quickly to reduce their verification and debug time before simulation, before synthesis, and definitely before burning chips in the lab.
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Emulation Platform
Veloce
The Veloce® Emulation Platform dramatically reduces risk in the verification of today’s complex SoCs and is a core technology in the Mentor Enterprise Verification Platform™ (EVP). Mentor’s software and application solutions and continual enhancements enable a comprehensive verification environment for IP, chip, and system level verification.
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Verification IPs
*AMBA AXI (AXI3, AXI4, Stream)*Open Core Protocol (OCP)*Advanced Peripheral Bus (APB)*Advanced High-performance Bus (AHB)
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IP QAM
SFT3332 (-D)
Hangzhou Softel Optic Co., Ltd.
SFT3332 (-D) IP QAM modulator is Mux-scrambling-modulating all-in-one device developed by SOFTEL. It has 32 multiplexing channels, 32 scrambling channels and 32 QAM (DVB-C) modulating channels, and supports maximum 1024 IP input through the GE port and 32 non-adjacent carriers (50MHz~960MHz) output through the RF output interface. The device is characterized with dual RF output ports which broaden the bandwidth for QAM carriers.
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Rapita Verification Suite
RVS
*Run requirements-based tests on your code *Produce coverage evidence including MC/DC from tests *Analyze execution time including worst-case timing on-target *Understand program scheduling behavior *Produce evidence for DO-178 and ISO 26262 certification
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Functional Verification
The Mentor Graphics Scalable Verification" is the most comprehensive EDA solution for functional verification, merging standards support, tools and a "design for verification" methodology to minimize verification cycles and costly design respins.
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IP QAM
SFT-IPSR3
Hangzhou Softel Optic Co., Ltd.
SFT-IPSR33 is a 2RU rack-mount IPTV streamer server. It is optimal for small and medium internet service providers to initial setup in large network.
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IP Gateway
SFT3503A
Hangzhou Softel Optic Co., Ltd.
SFT3503A Bidirectional IP Gateway is a head-end interface device which is used for DVB and Ethernet. It can be used both for a receiver and a lancers! On one hand, in the lancers part, this machine can be used for sending IP stream, turning the TS stream into IP Stream. On the other hand, in the receive part; this machine can be used for receiving IP stream, turning the IP stream into TS stream.
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IP Pulse
IP Compatible card with 4 programmable pulse generators. TTL or RS422 / RS485 compatible outputs. Programmable pulse - nS to seconds. Programmable count or free
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Software Escrow & Verification
NCC Group''s escrow and verification services assure the long-term availability of business critical software applications for end users and protect the intellectual property rights of software suppliers.
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Verification And Validation Services
Verification and validation services using innovative verification and validation techniques throughout the entire quality process for independent evaluation of performance and quality of product designed.
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Foundation IP
TSMC
Our Foundation IPs embed power management features (multi-Vt/multi-channel libraries, multi-VDD characterization, integrated power-switches, source-biasing…) which allow designers to explore the SoC architecture. Optimal configurations can be generated to meet the application’s Performance, Power and Area constraints. We also complement our offering to reach best-in-class Energy Efficient SoC by serving Always-On power-domains with a dedicated offer, optimized to achieve the ultra-low-power requirements of battery-operated devices in sleep mode.
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IP Cores
logicBRICKS IP Cores by Xylon - for applications including compact multilayer video controller, versatile video input, multiview 3D transformation engine, image signal processing (isp) ulstraHD pipeline, high dynamic range pipeline, scalable 3d graphics accelerator, DDR3 SDRAM Memory Controller, slave hssl controller, HDR image signal processing framework, video design framework for multi-camera vision applications, and more
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Hybrid Verification Platform
HES-DVM
HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.
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Envision Verification Analytics
Envision
IC Manage Envision Verification Analytics provides:* Anytime, anywhere, data-driven insights allow engineers and management to rapidly identify and address problem areas to meet tight schedules spanning simulation, formal and emulation tools.* Utilizes big data technology to deliver near real-time verification analytics across the verification tool spectrum, for any mix of EDA vendors* With 10-100X the speed of traditional methods you can instantly understand your verification progress, at local and global levels.* Visual analytics and interactive reporting for regressions, bugs and coverage* Verification results linked to relevant design activity to help identify and resolve bottlenecks
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Phase Verification Bridges
5002
Clarke-Hess Communications Research
The Model 5002 Phase Verification Bridge set comprises passive devices that are used in conjunction with Model 5500-2 Phase Standard and an output null indicator such as a true rms voltmeter, an oscilloscope or a wave analyzer to verify that the Phase Standard is continuing to operate within its specified phase accuracy limits.
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Verification Suite
Cadence is committed to providing industry-leading bare metal compute, the fastest verification engines, and the smartest verification applications so you can find and fix the most bugs per dollar compute per day.
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IP and Website Tracer
Visual IP Trace
Trace an IP address or web site back to its origin/location. There can be many reasons why anyone would want to trace an IP address or web site, everything from verifying a web sites location to avoid any potential phishing attempts, to verify a customers order, tracking a potential hack attempt and so on.
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X-Design and Verification System
Ascent XV
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.
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SoC Signoff & Structural Verification
Defacto’s STAR augments existing RTL verification flows by providing fully automated structural checks. Users can also define and build their custom checks.
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IP Gateway
SFT3508F
Hangzhou Softel Optic Co., Ltd.
SOFTEL SFT3508F IPTV Gateway is a device which is used for the protocol conversion scenarios and streaming media distribution scenarios. It can convert the broadcast network IP stream over HTTP, UDP, RTP, RTSP and HLS and TS file into HTTP, UDP, HLS and RTMP protocol. The system can achieve the integration by receiving a variety of commercial streaming media services. Also, the system can provide streaming media services directly.
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Verification IP's
SmartDV Technologies India Private Limited
We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP''s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
