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EBIRST 104-pin D-type Verification Fixture
93-022-101
Verification Fixture
The 93-022-101 104-pin D-type Verification Fixture is an accessory for the eBIRST range of USB controlled test tools capable of performing automated path resistance tests on Pickering Interfaces switching solutions. The tool simply interfaces with the switching system's connector so a test can be run using the supplied Windows-based software.
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Product
EBIRST 200-pin LFH Verification Fixture
93-002-101
Verification Fixture
The 93-002-101 200-pin LFH Verification Fixture is an accessory for the eBIRST range of USB controlled test tools capable of performing automated path resistance tests on Pickering Interfaces switching solutions.. The tool simply interfaces with the switching system's connector so a test can be run using the supplied Windows-based software.
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Product
HBM Verification Tester
HBM-VT
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High Power Pulse Instruments GmbH
- HBM pulse generator verification tester according ANSI/ESDA/JEDEC JS-001 up to ±10kV- To be used in HBM test and qualification labs for regular pulse generator specification compliance test in order to fulfill lab audit and certification requirements- Fully automatic compliance test and verification of HBM pulse generators regarding ANSI/ESDA/JEDEC JS-001 normative standard at 3 different load conditions: Short Circuit, 500 Ω, and a reference diode at VBR=15 V reverse breakdown voltage, including DC test- Parameter evaluation and verification of the transient HBM current waveforms: Peak Current, Rise Time, Decay Time, Maximum Ringing Current- Optionally available upgrade for all HPPI TLP-3010C, 4010C, 8010A, 8010C, HBM-TS10-A hardware systems in combination with HBM-S1-B (6kV) pulse generators (upgrade on request)- Fully automatic test report generation (PDF)- Electrically floating (no fixed system ground): The HBM loads, current sensor output, USB control interface and the enclosure are electrically floating. There is no limiting system ground which may introduce common-mode interference induced HBM current measurement errors.- Isolated industrial full-speed USB control interface- Isolated power supply derived from USB port- Compact size 126mm x 82.5mm x 44.5mm
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LSI Functional Verification Services
SpecInsight
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The keys to functional verification are “verification strategy” and “highly complete verification item extraction.” Our functional verification services emphasize highly complete verification item extraction while also generating test benches and functional scenarios, random verification, and even functional coverage to meet customer demands by providing these services from a wide variety of angles. By implementing functional verification on the RTL and C models designed by customers from a third-party perspective, we improve quality of customers’ circuits.
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Pegasus Verification System
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The Cadence® Pegasus® Verification System is a cloud-ready physical verification signoff solution, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved performance on DRC runs and reduces turnaround time from days to hours.
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MCB Thermal Verification Test Bench
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The test system is a special version of the thermal test test system in the sense that the test jig is primarily designed to hold and connect multi pole MCBs for thermal verification so that each pole can be verified to trip within the IEC time band after the MCB has been riveted. This test ensures the trip verification of MCB so as to trip all the 4 poles at once when overload is detected in one single pole. In short, this is a verification-only bench.
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Functional Verification Platform
Riviera-PRO
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Riviera-PRO™ addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.
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SoC Signoff & Structural Verification
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Defacto’s STAR augments existing RTL verification flows by providing fully automated structural checks. Users can also define and build their custom checks.
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Test Instrument for LAN Cabling Verification
MI 2016 Multi LAN 350
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High performance, multifunction test instrument for LAN cabling verification.
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Hybrid Verification Platform
HES-DVM
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HES-DVM™ is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-emulation standards like SCE-MI or TLM and newest FPGA technology, hardware and software design teams obtain early access to the hardware prototype of the design. Working concurrently with one another they develop and verify high-level code with RTL accuracy and speed-effective SoC emulation or prototyping models reducing test time and a risk of silicon re-spins.
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SoC Verification
TrekSoC
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TrekSoC automatically generates self-verifying C test cases to run on the embedded processors in SoCs. This verifies your chips more quickly and more thoroughly than an external testbench, hand-written C tests, or running only production code on the processors. TrekSoC's generated test cases target all aspects of full-SoC verification and work in a variety of different environments.
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Rapita Verification Suite
RVS
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*Run requirements-based tests on your code *Produce coverage evidence including MC/DC from tests *Analyze execution time including worst-case timing on-target *Understand program scheduling behavior *Produce evidence for DO-178 and ISO 26262 certification
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Test Program Quality Verification
CodeReport
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CodeReport is an easy-to-use application for verifying test program quality. CodeReport comes with many different, known quality screening rules that can be used to verify your test program is complete and ready for production. CodeReport also provides a graphical Rule Editor that allows you to create your own, custom rules. Ensure your coding standards and quality specifications are correct by generating your set of rules, checks, and screenings. Easily generate a detailed report for locating, correcting, and documenting the state of your test program. Quickly identify the tester hardware and instrumentation needed to run your program with the Tester Resource report. Save a session file to quickly return to your project after edits have been made or use the Session on other similar projects to transfer your configuration and custom rules.
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Multi Channel Optical Fibre Verification
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The multi-channel optical fibre test system is used in the development and qualification of single mode optical fibres. The fibres are exposed to environmental influences in a climatic chamber in order to analyse the data on insertion loss and reflection. In addition, the current temperature in the climatic chamber is documented. Insertion loss measurement is performed with the help of an optical power meter, laser sources and optical switches. An Optical Time Domain Reflectometer (OTDR) from Exfo is used for the reflection measurements. The system was designed for the simultaneous characterization of 15 sample fibres and one reference fibre.
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PAT and Installation Verification Unit
PowerCheck 1557
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The PowerCheck 1557 is a comprehensive PAT and installation verification checkbox. It carries out ongoing performance checks to ensure accurate measurement between calibration intervals. Fully tests Earth Continuity, Insulation Resistance, RCD Trip Time, RCD Trip Current, Loop, PE Conductor Current, Touch Current and Flash tests.
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Code Verification Systems for Machine-Readable Barcodes
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Nearly all products in today´s world provide coded information. Manufacturer data, product IDs, prices, item numbers and so on are translated into machine-readable barcodes. This information needs to be read at supermarket checkouts and at many places in operational goods logistics in an error-free, fast and reliable manner.
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Product
Static Design Verification
ALINT-PRO
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ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
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Matrix Code Verification Systems
REA VeriCube
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The REA VeriCube is a state-of-the-art matrix and barcode verification device which can be used across all industry sectors. Whether lying, standing or from top to bottom, virtually any test sample can be measured contact-free in the optimum measuring position. The measurement of optical codes in compliance with defined angles, distances and lighting allows accurate and reproducible measurement results and quality evaluations.
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EBIRST 50-pin D-type Verification Fixture
93-005-101
Verification Fixture
The 93-005-101 50-pin D-type Verification Fixture is an accessory for the eBIRST range of USB controlled test tools capable of performing automated path resistance tests on Pickering Interfaces switching solutions. Each tool simply interfaces with the switching system's connector so a test can be run using the supplied Windows-based software.
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Product
Online Lightning Verification Report
STRIKEnet®
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Vaisala STRIKEnet Provides the Most Reliable Lightning Location Technology for Objective Claim Verification. Vaisala STRIKEnet® is an online lightning verification report that objectively and accurately reports individual cloud-to-ground lightning strikes at a specific location on the date of loss.
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Process Verification with Augmented Reality
PVS AR
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Connected to our standard, open PVS (Process Verification System) platform, the new early adopter PVS AR system, allows users to do several things, not yet seen in the industry. First, by connecting to a wide variety of standard torque tools, standard PVS connectivity allows customer choice to pick the right tool for the right job, but now allows these tools to be used in an augmented reality framework.
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Phase Verification Bridges
5002
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Clarke-Hess Communications Research
The Model 5002 Phase Verification Bridge set comprises passive devices that are used in conjunction with Model 5500-2 Phase Standard and an output null indicator such as a true rms voltmeter, an oscilloscope or a wave analyzer to verify that the Phase Standard is continuing to operate within its specified phase accuracy limits.
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Verification IP's
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SmartDV Technologies India Private Limited
We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP''s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
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Portable Sequence Generator for Verification, Firmware & Validation
ISequenceSpec
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The complexity of modern SoC has raised the requirement for HW/SW co-simulation to catch the bugs from the early design stage. There is lack of common set of sequences which can be shared across the teams. ISepenceSpec helps design teams to generate the unified test and programming sequences in UVM and Firmware from the specification. ISequenceSpec uses the register information from importing the standard formats like IP-XACT, SystemRDL, XML. User can define the test sequences in a simple editor, and then generate the unified test sequences from verification to validation.
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Calibration and Verification Kits
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Flann offers a wide range of calibration and verification kits to suit many applications and price points. Compatibility with the vast majority of current and legacy VNAs can be provided. Additionally full customisation of our kits is possible to suit your requirements.
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Product
Verification Of Maximum Withdrawal Force Test Apparatus
IEC60884 FIG 18
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Shenzhen Chuangxin Instruments Co., Ltd.
IEC60884 FIG 18 verification of maximum withdrawal force test apparatusThis device complies with the requirements of GB 189.1-2008 Figure 18/19, IEC884 Figure 18/19, VDE0620, etc. It is suitable for checking the maximum force required to pull the plug out of the socket and the single pole pin pulled out from the socket assembly. Whether the minimum force required is within the range specified by
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Verification Suite
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Cadence is committed to providing industry-leading bare metal compute, the fastest verification engines, and the smartest verification applications so you can find and fix the most bugs per dollar compute per day.
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USB Analyzer for USB 3.2, USB4, and Thunderbolt 3 Testing & Verification
Voyager M4x
Analyzer
The industry’s most accurate and trusted USB analyzer platform now supports USB 3.2, USB4 and Thunderbolt 3 testing and verification. The legendary Voyager family combines best-in-class probe technology with industry-leading analysis software allowing designers and validation teams to debug problems and verify interoperability for next-generation USB systems.
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Functional Verification
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The Mentor Graphics Scalable Verification" is the most comprehensive EDA solution for functional verification, merging standards support, tools and a "design for verification" methodology to minimize verification cycles and costly design respins.
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Design Verification Editor Checker for SV/UVM
DVinsight
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DVinsight-Pro is a Integrated Development Environment (IDE) for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code. Design & Verification Engineers can create correct by construction DV code because DVinsight-Pro is a design verification editor checker that provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards.
