Lattice Semiconductor
Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.
- (503) 268-8000
- (503) 268-8169
- sales@latticesemi.com
- 5555 NE Moore Ct
Hillsboro, OR 97124
United States of America
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Product
Efficiency And Innovation, Squeezed Into One Tiny, Affordable Package
LatticeECP3
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*Up to 16 channels at 3.125 Gbps*800 MBps DDR3, 1Gbps LVDS*Up to 586 programmable sysIO buffers with support for PCI Express, Ethernet (GbE, XAUI, & SGMII), HDMI, SMPTE, Serial Rapid I/O, CPRI and JESD204A/B and more*Up to 150 k LUTs and 6.8 Mbits of SRAM*Wide array of packages as small as 10.0 mm x 10.0 mm with power consumption below 0.5 W
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Product
Best In Class, Easy To Use Design Software
Lattice Radiant Software
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Full Featured, Easy to Use Tool Suite - Lattice Radiant software offers all the best in class tools and features to help users develop their FPGA applications efficiently and effectively. Powerful yet intuitive tools provide fast design starts and precise implementation.
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Product
Advanced General Purpose FPGA
CertusPro-NX
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*Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).*Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.*Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.
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Product
PLD For Bridging, Infinitely Reconfigurable I/O Expansion.
MachXO
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*Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM*SRAM based logic can be reconfigured in milliseconds using JTAG port*IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS*Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting*Available in TQFP, csBGA, caBGA and ftBGA packages
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Product
Manage Power, Thermal & Control Planes In Real Time
Platform Manager 2 & L-ASC10
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*Full fault coverage – monitor all rails and temperature nodes*Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders*Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds*Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters*Reliable power & thermal fault detection in hardware, as opposed to software routines
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Product
Low-power, High-performance FPGA
iCE40 LP/HX
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*Available in three series with LUTs ranging from 384 to 7680: Low power (LP) and high performance (HX)*Integrated hard I2C and SPI cores that enable flexible device configuration through SPI*Match your preferred display to your application processor with interfaces such as RGB, 7:1 LVDS and MIPI DPI/DBI*Multi-source your image sensors by implementing flexible bridges supporting common interfaces such as HiSPi, subLVDS, LVDS and Parallel LVCMOS*Up to 128 kbits sysMEM™ Embedded Block RAM*Industry’s broadest range of 0.35 mm - 0.40 mm pitch BGAs fit in space-constrained applications
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Product
Bridging And I/O Expansion Versatility. Rapid Hardware Acceleration For Improved Signal Control.
MachXO2
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*Up to 256 kbits of user Flash memory and up to 240 kbits sysMEM™ embedded block RAM*Up to 334 hot-socketable IOs that avoid excess leakage*Programmable through JTAG, SPI, I2C or Wishbone*TransFR feature allows in-field design update without interrupting equipment operation*Programmable sysIO™ buffer supports LVCMOS, LVTTL, PCI, LVDS, BLVDS, MLVDS, RSDS, LVPECL, SSTL, HSTL and more
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Product
Futureproof Your Control PLD And Bridging Designs
MachXO3
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*Up to 9400 LUTs with up to 384 I/O pins*Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery*Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices*MachXO3LF includes programmable Flash and User Flash Memory (UFM)*Available in amazingly small (2.50 x 2.50 mm, 0.4 mm pitch) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch
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Product
Build FPGA-based Processor Systems In Minutes
Lattice Propel Design Environment
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Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.
